The invention relates to testing integrated circuits and in particular to a diagnostic utility for identifying defects and test pattern sensitivities in semiconductor logic.
Several design, test and diagnostic methodologies have evolved over the years in support of structural and functional test methods. Some of the integrated circuit designs integrate this support onto the device itself. These built-in self-test (BIST) and diagnostic functions are based on several design for test (DFT) techniques such as scan design (e.g., level sensitive scan design (LSSD) and general scan design (GSD)), logic and array built-in-self-test (LBIST and ABIST), on-product clock generation (OPCG), and others.
The LSSD test and diagnostic methodology has been widely used for many years. It is based on the concept of “divide-and-conquer” whereby large sequential logic structures are divided into smaller combinatorial partitions. The LSSD methodology is a system design and a DFT approach that incorporates several basic test concepts (e.g., scan design). In such a design most of the device's storage elements, such as latches or registers, are concatenated into one or more scan chains that are externally accessible via one or more serial inputs and outputs. Storage elements that are not in this category are usually memory or other special macros that are isolated and can be tested independently. The LSSD design methodology ensures that all logic feedback paths incorporate one or more of these concatenated storage elements, thereby simplifying a sequential design into subsets of combinational logic sections.
These basic design concepts in conjunction with the associated system and scan clocking sequences, greatly simplify the test generation, testing, and the diagnosing of complex logic structures. In such a design, every latch can be used as a pseudo primary input and as a pseudo primary output, in addition to the standard primary inputs and standard primary outputs, to enhance the stimulation and observability of the device being tested or diagnosed. Typically, LSSD latches are implemented in a configuration having master (L1) and slave (L2) latches where each master latch (L1) has two data ports that may be updated by either a scan clock or a functional clock, and each slave latch (L2) has one clock input that is out of phase with both the L1 scan and functional clocks. Scanning is performed using separate A and B scan clocks.
The strategy of diagnosing these LSSD circuits has been established and evolving for many years. The primary characteristic of deterministic or pre-determined LSSD patterns is that each pattern is independent from every other pattern and each pattern consists of stimulating primary inputs, clocking, load and unload of shift register latches, and primary outputs measure sequence. Such LSSD circuits may have thousands of patterns depending upon the size and structure of the logic. During diagnostics, one or more failing patterns are identified and fault simulation is performed on the failing pattern (load, primary inputs, system clocks, and unload sequence). The circuit states can be determined by analyzing and simulating the failing pattern load, primary inputs, system clocks and measures. Passing patterns may also be used to eliminate potential faults that the identified failing patterns marked as potential candidates.
Identifying the fault and pinpointing the root cause of the problem in large logic structures requires high resolution diagnostic calls. The high resolution diagnostic calls help to localize the defect(s), and to complete the physical failure analysis (PFA) defect localization. The resolution of current logic diagnostic algorithms and techniques depends on the number of tests and the amount of passing and failing test data available for each fault. A problem often encountered in testing, and the subsequent diagnosis, of very large-scale integration (VLSI) devices is the availability of effective test patterns for a broad range of modeled and un-modeled faults. The rapid integration growth of VLSI devices, associated high circuit performance, and complex semiconductor processes has intensified old and introduced new types of defects. This defect diversity and subtlety, accompanied by limited fault models, usually results in large, insufficient and ineffective diagnostic pattern sets. The results determined by the fault simulators are typically imperfect, in that they contain several (in many cases dozens) diagnostic calls that may need to be investigated in order to pinpoint the cause(s) of the failure.